1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having structures such as wirings and gate electrodes.
2. Description of the Related Art
In many cases, a semiconductor device is provided with a multilayer wiring structure in which a plurality of wiring layers is laminated. In the multilayer wiring structure, an insulating film in a lower layer for wirings is preferably planarized, and the CMP (Chemical and Mechanical Polishing) process is carried out for planarization of the insulating film.
The conventional method of manufacturing the semiconductor device is explained. FIGS. 1A and 1B are schematic cross-sectional views showing the conventional process of manufacturing a semiconductor device.
After semiconductor elements such as a transistor and a capacitor (not shown) are formed on a silicon substrate, primary insulating layer 25 is formed in order to ensure electrical insulation among the semiconductor elements. In the following, not limited to the silicon substrate, a term of “substrate” is used for those substrates including silicon substrates on which semiconductor elements and wirings are formed in the process of manufacturing.
Successively, on primary insulating layer 25, a film of tungsten that is 600 nm in thickness is deposited, and then wirings 24 of 600 nm in height are formed by the lithography process and the etching process. After that, LP (Low Pressure)-TEOS (Tetra Ethyl Ortho Silicate) oxide film 23 that is 300 nm in thickness, which is conducive to embedding, is formed so as to cover wirings 24. Then, on LP-TEOS oxide film 23, plasma oxide film 22 having a thickness of 700 nm is formed (FIG. 1A).
Since the cross-sectional view shown in FIG. 1A is a schematic view showing a cross-section taken along a line passing the center of the substrate, both ends of the cross-section in FIG. 1A are ends of the substrate and the central part of the cross-section is in the vicinity of the center of the substrate. To simplify explanations, in this schematic view, two peripheral regions and one central region are shown as formation regions of semiconductor devices, and cross-sections of three wirings are shown in each formation region. Also, the formation region of the semiconductor device approximately corresponds to the size of one chip.
As is apparent from this schematic view, in the region where the wiring formation density is high like as in a chip, LP-TEOS oxide film 23 is buried also between the wirings, and therefore the surface of plasma oxide film 22 formed thereon is flat. On the other hand, between the chips, the wiring formation density is low, and therefore LP-TEOS oxide film 23 is formed along the upper face of primary insulating layer 25. Accordingly, step heights corresponding to the heights of wirings 24 are generated in the vicinity of the peripheries of the chips. The step shapes appear on the surface of plasma oxide film 22 formed on LP-TEOS oxide film 23.
As shown in FIG. 1A, step heights corresponding to the heights of wirings 24 are formed on the surface of plasma oxide film 22. When wirings are formed on plasma oxide film 22, as it is, a problem occurs in that wiring materials remain as spacers on side walls of the step heights in the regions where the wiring materials must be removed. For that reason, as shown in FIG. 1B, silicon oxide film is polished by the CMP process until the step heights in plasma oxide film 22 are eliminated.
In the CMP process, the process condition is determined so that the polishing amount is about 500 nm on average on the surface by performing the process for a predetermined time. The value of amount that is polished is obtained from the measurement for the thickness of plasma oxide film on monitor wafer in which the film is formed on a silicon substrate having no patterns such as wirings thereon (hereinafter, called monitor wafer).
When the CMP process is performed, there is a problem in that scratch 26, namely, slight flaw, is generated in the surface of the film to be polished. A sight scratch in which elements such as width, length, and depth are smaller than 200 nm has little effect on a product, as it is, and has frequently little effect on the production such as the quantity yields of products that can be manufactured. On the contrary, a scratch larger than 200 nm cannot be disregarded. Japanese Patent Laid-Open No. 2002-270557 discloses measures against large scratches, wherein an insulating film is formed after the CMP process, and then etch-back for etching the insulating film evenly is performed so that the insulating film is buried into the scratches.
In the above-described CMP process, caused by unevenness of the surface in the CMP process, the polishing amount is smallest in the center of the substrate, and is largest in the periphery. When the process is performed while the polishing amount is set to 500 nm, the actual amount that is polished is about 450 nm in the center of the substrate and is about 550 nm in the periphery. These values of amounts that are polished are obtained from the measurements of thickness of film on monitor wafer. Therefore, variations of ±10% are generated in the amount that is polished in the substrate. Accordingly, when the method disclosed in the above-described Patent Document is performed, the insulating film is buried into the scratches, the variations in the amount that is polished by the CMP process are allowed to be transferred to the silicon oxide film for covering the wirings.
Further, when the etch-back amount in the periphery is larger than that in the center, planarization becomes still worse. When planarization becomes worse, at the time of forming wirings thereafter, variations in the photoresist size of the lithography process in the substrate increase, and variations in etching of the etching process in the substrate increase. As a result, size variations in wirings in the substrate increase, and there is a possibility that production yields may be reduced.